Field-effect transistors



Oct. 10, 1967 w. F. PARMER 3,346,786-

FIELD-EFFECT TRANSISTORS Y Original Filed Aug. 14, 1962 ATTORNEY UnitedStates Patent 3,346,786 FIELD-EFFECT TRANSISTORS Will F. Parmer, Dallas,Tex., assignor to Texas Instruments Incorporated, Dallas, Tex., acorporation of Delaware Continuation of application Ser. No. 216,843,Aug. 14, 1962. This application July 26, 1966, Ser. No. 568,056 9Claims. (Cl. 317-235) ABSTRACT OF THE DISCLOSURE The invention relatesto a field effect transistor having a gate electrode on opposite sidesof the channel. The two gates are in a single region of oneconductivity-type material, opposite to that of the channel, and theregion extends from one gate to the other interconnecting them.

This application is a continuation of application No. 216,843, filedAug. 14, 1962, now abandoned.

Field-effect transistors are preferably fabricated in the double-gategeometry since this configuration offers the advantages of highertransconductance and lower pincholf voltage. This results from the factthat two gates provide two depletion regions moving toward one anotherrather than a single depletion region moving toward the surface of thesemiconductor. It is usually desirable to connect the two gateselectrically, but heretofore this connection is made by providingelectrical contacts on both gates and connecting a lead between thecontacts. This adds several steps to the fabrication procedure,resulting in more chances for mistakes and reducing yield. Also, thecompleted devices have inherently lower reliability due to theadditional structural elements. The necessity of making electricalconnection to the second gate requires that the dimensions of the gatebe adequate to facilitate depositing contact material and bonding a leadto the contact. This needlessly expands the gate area, resulting in anincrease in the capacitance between the gate and the other regions,limiting the frequency response of the device. Also, the length of thechannel from source to drain is preferably quite short, but thisrequirement is inconsistent with the necessity for placing an electricalcontact on the gate.

Accordingly, it is the principal object of this invention to provide adouble-gate field-effect transistor adapted for fabrication by diffusiontechniques which does not require external connections between the twogates. An additional object is to provide an improved field-effecttransistor. Another object is to provide a diffused field-effecttransistor having internally-connected gates. A further object is toprovide a simplified technique for fabricating semiconductor devicessuch as field-effect transistors.

In accordance with this invention, a field-effect transistor isfabricated by a double-diffusion technique wherein the channel is firstdiffused into a wafer of semiconductor material and then the top gate isdiffused into the channel region. The dilfusion patterns are such thatthe top gate region produced by the second diffusion will be ohmicallyconnected within the semiconductor crystal to the un-diffused bulk ofthe wafer, the latter portionforming the second gate. Thus, the two gateregions are internally connected together without requiring anadditional bonded contact and lead.

The novel features, objects and advantages of the present invention willbecome readily apparent from the following description when taken inconjunction with the appended claims and detailed drawings wherein:

FIGURE 1 is a greatly enlarged pictorial view of a field-eifecttransistor constructed according to this invention;

FIGURE 2 is a sectional view of the device of FIG- URE 1 taken along thelines 22;

FIGURE 3 is a greatly enlarged, fragmentary, pictorial view in sectionof the active area of the device of FIG- URE 1, also viewed along thelines 22;

FIGURE 4 is a pictorial view in section of another embodiment of afield-effect transistor constructed according to this invention.

With reference to FIGURES 1 and 2, a field-effect transistor of thedouble-diffused planar type having a P- type channel andinternally-connected gates is illustrated. This device is constructed onan N-type silicon Wafer 10, which forms the lower gate, and includes adiffused 'P- type region 11 forming channel, source and drain regions. Asource contact 12 and a drain contact 13 are positioned on oppositesides of the region 11. A diffused N-type region 14, forming the topgate, is provided to separate the source and drain, and to define thelimits of the P-type channel. According to this invention, this seconddiffused region 14 extends beyond the ends of the P-type diffuse-dregion 11 and so makes ohmic contact to the N-type parent wafer 10.Thus, the top gate region 14 and the bottom gate defined by the wafer 10are connected together, and so a single gate connection is all that isnecessary. This gate connection is made by bonding or soldering the backof the wafer 10 to a conductive plate 15 which may be a conventionaltransistor header. The source and drain contacts 12 and 13 may haveenlarged areas 16 and 17 to which leads 18 and 19 may be easily bonded.These leads would be connected to studs in the transistor header inaccordance with conven tional packaging techniques. The device ispreferably fabricated by oxide masking techniques and so an oxide layer20 remains on the top surface of the silicon wafer to protect the P-Njunctions.

A method for fabricating the devices illustrated in FIG- URES 1 and 2may best be described with reference to FIGURE 3, which is a greatlyenlarged sectional view of a small portion of the wafer 10 in the activearea. The original wafer, from which many of the devices may be -madesimultaneously, may be doped with phosphorus upon growing to a levelwhich produces a resistivity of greater than about one ohm-cm; The topsurface of the wafer 10 is first polished and cleaned, then a siliconoxide layer is applied by passing steam over the heated water, forexample. A generally rectangular opening 22 defining the outline of theregion 11 is then formed in the oxide by photo-resist maskingtechniques, exposing the bare silicon within this area. This opening 22could be perhaps 60 mils long by 6 mils wide, for example. The region 11is thereafter formed by depositing boron on the surface of the wafer andthen heating to a temperature of about 1200 C. or over for a time'sufiicient to provide a junction depth of about 0.15 mil. At the sametime, an oxide coating 23 is formed over the area exposed by the open-.ing 22. A second photo-resist masking step is then performed to definean elongated narrow opening 24 above What will be the region 14,exposing a narrow area of the surface of the wafer perhaps 0.5 mil wideand 65 mils long. The major portion of the length of this opening 24,more for several hours or until a junction depth of about 0.10 milresults. The junction depths are of interest primarily due to the factthat a channel thickness of about 0.05 mil provides particularlyadvantageous characteristics. During the N-type diffusion, more oxide isformed on the wafer surface, and covers the region 14 or opening 24.This oxide coating is of course left on the device (a to protect thesurface. The source and drain contacts 12 and 13 are then made byselectively etching holes in the oxide coating and then evaporatingaluminum onto the surface and removing the unwanted aluminum by maskingand etching.

With reference to FIGURE 4, there is shown a fieldeffect transistor ofcircular geometry which employs the internally-connected gates of thisinvention. Assuming that an N-type channel is desired, a P-type siliconwafer 30 is utilized, and an N-type diffuse-d region 31 is formed in thetop surface by oxide masking techniques comprising opening a circularhole 32 in an oxide coating 33 and diffusing from a deposited phosphorussource. A very small portion of the oxide coating 33 is left intactwithin the area exposed by the opening 32, providing a diffusion maskfor a small area under that will subsequently be the top gate. Thissmall masked area will remain undiffused and a portion 34 of the parentmaterial will extend to the surface. After the first diffusion step,which also forms another oxide coating 35 over the previouslyexposedsurface, a ring-shaped opening 36 is cut in the oxide by photo-resistmasking and etching. Boron is deposited on the top surface of the waferand difiused through the ring-shaped opening 36 to form a ring-shapeddiffused region 37 which is the top gate. This region 37 is spaced fromthe P-N junction outlining the region 31 by perhaps 0.05 mil, except forthe portion overlying the un-diffused region 34. Here the P-typematerial of the wafer 30 and the P-type diffused region 37 overlap,providing the desired internal connection of the gates. Simultaneouslywith the P-type diffusion, an oxide coating is formed over the opening36, and this coating remains on the device for surface passivation. Acircular contact 38 and a ring-shaped contact 39, providing the sourceand drain connections are then applied by removingcorrespondingly-shaped areas of the oxide coating 35 and depositingaluminum in the exposed surface areas. The

single gate connection is made by bonding the wafer 30 to a conductiveplate (not shown) such as a transistor header as suggested above.

While the device of FIGURE 4 is of circular geometry, the principlescould be equally well applied to any closed or concentric configuration.Thus, a rectangular pattern wherein the top gate encloses the source ordrain could be fabricated in the same manner as described above, theonly difference being in the shapes of the masks used. Of course, eitherof the preferred embodiments set forth above could have either -P-typeor N-type gates.

It is seen that the basic feature of this invention is the concept ofmasking the channel diffusion in such a fashion that a portion of theparent material remains un-diffused. The gate diffusion is then made sothat impurities are diff-used into both the channel region and into aportion of the parent material remaining on the surface of the wafer. Ofcourse, in speaking of the parent material in this sense, it iscontemplated that this may as well be itself a diffused region, in whichcase a triple-diffused device would be provided. Also, even though theexamples given above describe only diffusion for making the top gateregion, the concepts of this invention, in its broadest aspects, maywell be applied to a double-gate field-effect transistor wherein the topgate is provided by an alloyed region.

Accordingly, although the invention has been described with reference toillustrate embodiments, this description is not meant to be construed ina limiting sense. It is of course understood that various modificationsmay be made by persons skilled in the art, and so it is contemplatedthat appended claims will cover any such modifications as fall withinthe true scope of the invention.

What is claimed is:

'1. A field-effect transistor comprising a semiconductor body of onetype of conductivity, a first region within said semiconductor body andadjacent a major face thereof comprised of semiconductor material of theopposite conductivity type from said semiconductor body, said firstregion being separated from the rest of said semiconductor body by a P-Njunction, a second region having the same conductivity type as saidsemiconductor body extending across said first region and separatingsurface portions of the said first region adjacent said major face intotwo distinct parts and connecting with said semiconductor body, saidfirst region comprising a channel, between said body and second region,connecting said parts, and contacts connected to said two parts of saidfirst region and said semiconductor body.

2. A field-effect transistor comprising a semiconductor substrate havingat least one substantially flat major face, a first region comprisingsubstantially the entire portion of said substrate containing a one-typeconductivity, a second region formed in said major face of saidsubstrate within said first region of an opposite type conductivity thansaid first region, said second region separated from said first regionby a P-N junction which terminates at said major face, a third regionhaving the same conductivity type as said first region extending throughsaid second region and electrically connecting with said first regionwithin said substrate, said third region being separated from saidsecond region by a P-N junction which terminates at said major face,said first region and said third region forming the gates of saidfield-effect transistor and said second region forming the source,channel and drain of said field-effect transistor.

3. A field-effect transistor comprising:

(a) a wafer of monocrystalline semiconductor material, the major bulk ofthe wafer being composed of semiconductor material of oneconductivity-type and providing a first gate,

(b) a first region of the wafer adjacent a major face composed ofsemiconductor material of the opposite conductivity-type and providing asource, a drain and a channel, the first region being separated from thebulk of the wafer by a P-N junction which extends to the major face anddefines an enclosed surface area,

(c) a second region of the wafer adjacent said surface composed ofsemiconductor material of said one conductivity-type and providing asecond gate, the second region being contiguous to the first region butseparated therefrom by a P-N junction,

((1) and at least one portion of the wafer contiguous to both the secondregion and the major bulk formed by coextensive parts thereof composedof semiconductor material of said one conductivity-type and effective toprovide internal ohmic connection between the first and second gates,the second region being spaced from the first region by said channel ofthe first region except for said portion.

4. A field-effect transistor according to claim 3 wherein said portionis outside the enclosed surface area.

5. A field-effect transistor according to claim 3 wherein said portionis within the enclosed surface area.

6. A field-effect transistor comprising:

(a) a wafer of monocrystalline semiconductor material,

(b) a first region of the wafer adjacent a surface thereof composed ofsemiconductor material of one conductivity-type, said first regionproviding a first gate,

(c) a thin second region of the wafer adjacent said surface composed ofsemiconductor material of the opposite conductivity-type and providing asource, a drain and a channel, the second region being contiguous to thefirst region but separated therefrom by a P-N junction which extends tosaid surface and defines an enclosed surface area,

((1) a narrow elongated third region of the wafer adjacent said surfacecomposed of semiconductor material of said one conductivity-type andproviding a second gate, the third region being contiguous to the secondregion but separated therefrom by a P-N junction,

(e) and at least one connecting portion of the wafer contiguous to boththe first and third regions formed by coextensive parts thereof, theconnecting portion being composed of semiconductor material of said oneconductivity-type and effective to provide internal ohmic connectionbetween the first and second gates, the third region being spaced fromthe first region by said channel of the second region except for saidconnecting portion.

7. A field-effect transistor according to claim 6 wherein two of theconnecting portions are provided externa of the enclosed surface area.

8. A field-effect transistor according to claim 6 wherein one connectingportion is provided within the enclosed surface area.

9. A field-effect transistor comprising:

(a) a wafer of monocrystalline semiconductor material,

(b) a first region of the wafer adjacent a surface thereof composed ofsemiconductor material of one conductivity-type, said first regionproviding a first gate,

(c) a thin, diffused, second region of the wafer adjacent said surfacecomposed of semiconductor material of the opposite conductivity-type andproviding a source region and a drain region connected within the waferonly by a thin channel region, the

second region being contiguous to the first region but separatedtherefrom by a P-N junction,

((1) a narrow, elongated, third region of the wafer adjacent saidsurface composed of semiconductor material of said one conductivity-typeand providing a second gate, the third region overlying the channelregion and being contiguous thereto but separated therefrom by a P-Njunction,

(e) and at least one connecting portion of the wafer contiguous to boththe first and third regions formed by coextensive parts thereof, the atleast one connecting portion being composed of semiconductor material ofsaid one conductivity-type and effective to provide internal ohmicconnection between the first and second gates.

References Cited UNITED STATES PATENTS 2,648,805 8/1953 Spenke et a1.317235.21 2,805,397 9/1957 Ross -1--- 317235.21 2,869,054 1/1959 Tucker317--235.21 3,025,438 3/1962 Wegener 317--235.21 3,152,294 10/1964Siebertz et a1. 317-235.21 3,183,128 5/1965 Leistiko et a1 317-23521JAMES D. KALLAM, Primary Examiner.

1. A FIELD-EFFECT TRANSISTOR COMPRISING A SEMICONDUCTOR BODY OF ONE TYPEOF CONDUCTIVITY, A FIRST REGION WITHIN SAID SEMICONDUCTOR BODY ANDADJACENT A MAJOR FACE THEREOF COMPRISED OF SEMICONDUCTOR MATERIAL OF THEOPPOSITE CONDUCTIVITY TYPE FROM SAID SEMICONDUCTOR BODY, SAID FIRSTREGION BEING SEPARATED FROM THE REST OF SAID SEMICONDUCTOR BODY BY A P-NJUNCTION, A SECOND REGION HAVING THE SAME CONDUCTIVITY TYPE AS SAIDSEMICONDUCTOR BODY EXTENDING ACROSS SAID FIRST REGION AND SEPARATIONSURFACE PORTIONS OF THE SAID FIRST REGION ADJACENT SAID MAJOR FACE INTOTWO DISTINCT PARTS AND CONNECTING WITH SAID SEMICONDUCTOR BODY, SAIDFIRST REGION COMPRISING A CHANNEL, BETWEEN SAID BODY AND SECOND REGION,CONNECTING SAID PARTS, AND CONTACTS CONNECTED TO SAID TWO PARTS OF SAIDFIRST REGION AND SAID SEMICONDUCTOR BODY.